SP0-S | Radiation Tolerant 3U CompactPCI SBC

NXP PowerQUICC®III MPC8548E Processor

The 3U CompactPCI SP0-S is a space-rated single-board computer (SBC), based on NXP’s PowerQUICC®III MPC8548E system on chip with an e500 processing core. The SP0-S includes several performance enhancing improvements over previous designs, including an SDRAM memory upgrade to the DDR2 with 20% higher bandwidth at lower power dissipation.

Also added are three rad-hard, on-board temperature sensors as well as six microcontroller-based A/Ds that monitor the board’s 3.3 VDC input voltage and five of the internally generated CPU core and I/O voltages. Fully tested and characterized to over 100 krad (Si) and latch-up immune to > 65 MeV-cm2/mg, the SP0-S is ideal for high performance high altitude, NEO, LEO and GEO missions.

  • Space-qualified 3U CompactPCI SBC
  • PowerQUICC-III MPC8548E @ 1.0 GHz
  • 400 MHz Core Complex Bus (CCB) Speed
  • One (1) Standard 32bit/33 MHz PMC Site
  • PICMG 2.0, Rev. 3.0 Compliant
  • System Controller or Peripheral
  • 1GB of DDR2 at 400 MHz with ECC
  • 1GB User Flash Memory with ECC
  • Redundant 512KB EEPROM Boot Memory
  • One (1) or Two (2) Gb Ethernet Ports
  • Three (3) Async Serial RS-422 Ports
  • Five (5) Single Ended TTL I/O lines
  • Four (4) High Performance DMA Engines
  • Four (4) 32 bit Timers (Internal to the CPU)
  • Three (3) Watchdog Timers
  • 1PPS port for Timing Synch.
  • Three (3) On-board Temperature Sensors
  • Six (6) on-board A/D voltage monitors
  • Options for Front Panel Connectors
  • VxWorks 6.7 or 6.9 RTOS Support
  • Optional VxWorks 7.0 or ARINC 653
  • Linux 4.14 and Xenomai/Cobalt Linux with NASA cFS (core Flight System)
  • Available in Conduction Cooled
  • Versions Series 100, 200 and 500
  • S500 utilize Hypertronics Hypertac cPCI backplane connectors
  • LEO, MEO and GEO Mission Options

TMSP0

The TMSP0 Rear Transition Module provides a standard direct connection to all SP0- I/O interfaces and is intended for use in commercial air-cooled chassis.

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